That’s my confusion as well…If I want to run the ADC and the DAC at the same sampling rate (~200 MHz) it appears that the reference design always divides the input clock by 2. There is a MMCM_CLKIN1_DIVIDE parameter which is set to 2. So, I was assuming that the DAC Clock Input to the FPGA was running at 2x the expected sampling rate. Not sure if my assumption is correct…I don’t have a lot of insight into the clocking scheme external to the FPGA. I do need to run at 2.2 – 2.4 GHz at the Input/Output of RF chain…
Thanks!
Stu