Hi,
I'm prototyping an ultrasound scanner based on AD9272 and I've got some
problems/questions. First, I would like to tell you some details about my project:
1) HV TX circuitry is not assembled yet on my PCB, it will be the next step on
prototyping. First I want to have RX channel working fine.
2) My design is as follows: 80MHz generator => AD9512 (clock distribution chip/OUT4
output used[default devided/4]) => AD9272-80 => FPGA (XC6SLX45-CSG324)
deserializer+post processing.
3) Only one channel of AD9272 is used now. All other 7 unused analogue LIx/LGx
inputs are tied to GND.
4) LVDS outputs from AD9272 D+/-,Frame+/-,BitCLK+/- => FPGA deserializer + post
processing.
5) TGC shape is software controlled: PC (software shape defined) => USB (FT2232H)
=> FPGA => AD7302=> AD9272 TGC input. This controll signal looks perfect on scope.
6) AD9512/AD9272 share the same SPI signals: SDIO (used only for write) and SCLK.
All the above and CSB1 (AD9512) and CSB0 (AD9272) are driven as follows: PC
(software) => USB (FT2232H) => FPGA => AD9512/AD9272.
=========================
And now some scope observations and some problems:
1a) First I want to clock the AD9272 with 80MHz, then I have to bypass the default
/4 divider on AD9512. I pull the CSB1 low (by software) and then (pseudo code):
- write(0x53,0x80) // bypass divider //
- write(0x5A,0x01) // update the changes //
This work perfect, any other SPI instructions on AD9512 work fine.
2a) And now here is the problem!!
- CSB1 high (AD9512 disabled), CSB0 low (AD9272 enabled). Scope shows it's OK.
- write(0x0D,0x09) // 1/0-bit toggle // output test mode
- write(0xFF,0x01) // update //
======================
Doesn't work!! Scope observations:
1b) When I touch the finger to the AD9272 input, then any deserlialized bit output
(11:0) from the FPGA goes insane!!
2b) I'm not sure that my deserializer design is perfect. However, as I do the
procedure (2a), touch the finger to the AD9272 input, and observe on scope the
insane changes on any bit (1b) , it means the device is still working in its
default mode.
3b) Even if my FPGA deserializer is not OK, then the analogue input finger touching
should not the FPGA outputs.
================
Anyway, please pay your attention at:
1c) On Power-up, touching the finger to the input makes insane changes on any bit
on the deserializer output.
2c) Upon a procedure (2a), result is (1c).
3c) Please!! Pay your attention on 3b !!
What a hell do I do wrong??
Regards,
Mariusz