Hello Gunter,
I've finally figured the problem out.
I design my FPGA to follow the datasheet (Rev B) requirements
tvsu = 1.8ns
tvhld = 1.3ns
to accomplish this, I had a PLL apply a 150 degree phase shift on the clock; which is roughly 2.8ns at 148.5 MHz
Reading further, it sounds like the ADV7513 applies a default clock delay of -1.2ns (register 0xBA, = 0001_0000)
So in essensce my clock would be delayed 4 ns total (2.8 outside , 1.2 inside)
After I change the 0xBA to 0111_0000; it appears to be working correctly at 1080p60.
There appears to be different values in the datasheet vs. the hardware user guide for tvsu and tvhld.
What is the required setup time and hold time if the ADV7513 is not applying any internal delay?
Regards,
Matt Ferraro