HI Caleb Pellerin,
Can you send me scope shots of your interface lines?
Regarding why DIN should be kept high, there's a document on this which states:
“The interface implementation on these converters is basically a state machine that counts clock pulses and defaults to waiting
for a write to the communications register when an operation is complete. When the communications register is written to,
specifying a write to the Setup register for example, the ADC knows that 8 clocks are required to clock in the data. Spurious
clocks on the interface cause the interface to lose synchronisation, leading to wrong registers being addressed and thereby
corrupting the interface. Tying DIN high between write operations prevents invalid data being written to the ADC.
The first bit in the write operation to the communications register is a gating bit that must be ‘0’ to allow the remaining 7 bits
to be clocked into the register to specify the next operation. To avoid the possibility of interface issues due to spurious clocks,
it is advised to take the DIN line of the converter to a logic high as soon as each write to the converter is complete. Since
these converters default to waiting for a write to the communications register, taking DIN high when it has completed a
sequence prevents invalid data being written to the communications register if spurious clocks occur. At this time, the ADC
is waiting for a zero on DIN before it enables further data into the register. If the part is set up for a write to the
communications register with the DIN high, it is effectively immune to spurious serial clocks. This will not prevent spurious
clocks received during a write operation from corrupting the interface.”
In summary, DIN is kept high so as to avoid writing to the ADC when spurious pulses on the SCLK occur. For reference, please see attached.
Thanks and Best Regards,
Chris