The difference in PLL loop bandwidths could be related to the reference clock frequency used vs PLL multiplication value (N) setting. For example, if the REF CLK is 100MHz and N=25 vs 50MHz and N=50 to produce the ~2.5GHz PLL output frequency this would have an ~2x impact in PLL loop bandwidth if all other parameters (i.e. charge pump current) stay at the same settings.
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