Hi Bill,
Below is the interface circuit on Ctl A and Ctl B inputs of the HMC347.
On each of the control paths, CTRLA and CTRL B, the series R is 1250-ohm and the C is the internal FET’s channel capacitance, 1.5pF. R is connected to the Vctl input pin.
Attached is the typical RF settling time, time measured from 50% of triggered Vctl to >90% of RF out, of the HMC347. The performance was evaluated on HMC347 in LP3 package, but should closely represent the performances on the HMC347 in die and other package forms. The data report also includes our recommendation on forward biasing/gate lag solution to improve the RF settling time of the HMC347.
Please contact me if you have other questions.
Best Regards,
MN