hello when i debug ad9984a i sample vsync and hsync and data in fpga ,case 1920*1080 the data valid is not 1920 ,i don't know why , and i fond the fornt time sync time do not Consistent with vesa timing ,wish your help
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hello when i debug ad9984a i sample vsync and hsync and data in fpga ,case 1920*1080 the data valid is not 1920 ,i don't know why , and i fond the fornt time sync time do not Consistent with vesa timing ,wish your help