Hi:
we are have problems to get a ADV202 working. After a whole week struggling I'm pretty sure I need help from you genius. I promise I will write a detailed document to describe all my experience to this community for other people's reference.
This is our system:@@@@@@@@@@@@
Input:
FPGA continuously generate 320*256 video data to VDATA port on ADV202,with HVF signal, gray level(Y signal only),8 bits. Only one filed, progressive.
NIOS core(a small MCU) in FPGA to set parameter for ADV202,
Output:
32 bits burst DMA mode on HDATA port for compressed data output.
Problem:
FPGA can get 34 DREQ0 form ADV202, with 32 bits data width and 64 burst length this would be 8704 bytes, matches the setting in compressed data quality. BUT the output data is always 0.
Parameter setting:
////DIRECT REGISTER SETTING///////
ADV_PLLHI=0x0008
ADV_PLLLO=0x0004
delay_us(20);
ADV_BOOT=0x008A//software reset
delay_us(20);
ADV_MMODE=0x000A//4 bytes self-increase ,32bits data width
ADV_BUSMODE=0x000A//32bits Hdata DMA
/////LOAD FIRMWARE ////
the firmware loading should be ok, software flag will be 0XFF82
////FIRMWARE PARAMETER/////////
ADV_IADDR=0x00057F00
ADV_IDATA=0x04000203// 0x00-0x03 IDATA picture formate:custom;8bit; 2leve wavelet; Unipolar C, Unipolar Y
ADV_IDATA=0x00000000//0x04-0x07 CodeBlock = 32 * 32; 9/7wavelaet; capture all fields; no attribute data out
ADV_IDATA=0x01001F5C// 0x08-0x0B compressing quality by size, output size = 8k
ADV_IDATA=0x00410001// 0x0C-0x0F :LRCP; external HVF pins, field falling, HSYNC falling, VSYNC falling, VCLK rising, J2C format.
////INDIRECT REGISTER////
PMODE1=0x0004 0000//input VDAT 8bits, 0-255
XTOT=0x0140 0000//320 pixels
YTOT=0x0100 0000// 256 lines.
F0_START=0x0001 0000//F0 only
F1_START=0x0000 0000//F1 disable
V0_START=0x0001 0000//V0_Start from the first pixel
V1_START=0x0000 0000);//V1_Start disable
V0_END=0x0100 0000);//256 active lines
V1_END =0x000 00000);//disable
PIXEL_START=0x0001 0000);//start from the first pixel
PIXEL_END=0x0140 0000);//320 active pixel.
(We tried to add some blanking by following parameter but doesn’t work.
V0_END=0x00C8 0000);//200 active lines
PIXEL_END=0x0100 0000);//256 active pixel. )
PMODE2=0x0035 0000//Y and C 0-255, field falling, HSYNC falling, VSYNS falling ,VCLK rising
VMODE=0x0886 0000//CNT_RD_EN=1,PRGRSV_SCN=1, RAW_MODE=0 for HVF mode, HOST_MODE=0, DUAL_LINE=0,MP656=1 for external HVF, ENC_DEC=1 , MAS_SLV=0 for slave;
EDMOD0=0x00D2 0000);//DR0PULS=0, DMBL0=011 for burst length 64, DMMOD0=010 burst DMA mode,DMSEL0=01 for compressed data.
////read SWFLAG////
ADV_EIRQIE=0x0000 0400
read EIRQFLG==0x400;
EDMOD0=0x00D3 0000
read SWFLG==FF82;
////clear IRQ and run////
EIRQFLG=0X0000FFFF;
/////////END////////
Timing:
this is a snapshot of reading data on HDATA which is always 0xFFBE9FEF, sometimes it is always 0, I think this is meaningless.
DREQ0 asserted by ADV202, DACK0, RD responded by FPGA,
FPGA streaming input data on VDATA.
Any advise is appreciated.
Thank you!
