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Re: AD9139, DAC latency from input to output

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Hi jerryguo,

 

Please let me ask you a few question in regard to this issue, after trying it in the customer's site.

 

Thank you very much and basically this suggested steps are working well.

However, the customer found Reg [0x5].bit5 of one device often doesn't become 1, in step 3. of your instruction. 

( 3.  After Reg [0x5].bit5 become 1, ... )

 

This failure is not always occured even in this individual.  Sometimes it occurs frequently, assuming around 50% failure if frequent. It is also said, temperature may be related and higher temperature push up failure rate.

 

As long as the customer did, by retrying same steps from the beginning,  Reg [0x5].bit5 successfully becomes 1.

 

The customer is asking,

Q1)  Is it able to guarantee one retry has to clean up this issue ? or have to repeat retry until Reg [0x5].bit5 becomes 1 ?

 

Q2)  Is this issue(sometimes Reg [0x5].bit5 doesn't become 1) envisioned on the design of AD9139 ?

 

Q3)  The customer doesn't use SYNC, however the procedure use SYNC LOCK bit for judging.

  Could you please provide more explanation about this usage of SYNC LOCK when NOT using SYNC_ENABLE ?

 

Q4) Maybe related to Q3, when observing above failure, the customer see Reg [0x5].bit6 (SYNC_LOST) is 1.

  Is this also question by the customer why SYNC_LOST in case of SYNC_ENABLE=0, please could you explain ?

 

Sorry to ask many and in detail, but your helps are always very much appreciated !

 

Best Regards,


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