ADV7181D DDR mode (register value of PCL)

Hello,

I have one questions about ADV7181D.

How should we set  register value of PCLK  because of using table 53: DDR Bus Assignment  ?
Is its value intial value ?

FPGA which receives data from ADV7181D is designed as below
latch G[3:0]B[7:0] at risginh edge and R[7:0]G[7:4] at falling.
Abeve is reffered to Table 53: DDR Bus Assignment described in ADV7181D_Manual_Rev0.pdf 9.3.1 Pin Assignment（P190）.

Then output waveform of our board is  below  and below result is opposite result of table 53.
（0x37）=0x01（initial value）,
（0x89）=0x08
（0xC9）=0x08

So, we see the same result as Table 53: DDR Bus Assignment  when we add setings of PCLK（0x37）=0x00（Invert LCC output polarity）.

Regards,