Hi,
Each time that the gain is changed, an internal FS calibration should be performed to calibrate the gain error due to the PGA. An internal FS calibration is not required when the output data rate is changed.
Can you repeat your first test and include the internal FS calibration when the gain is changed.
Regarding your second test, the values written to the configuration register are incorrect – the channel selected is not a valid channel.
Regarding signals which are out of range, the ADC will generate a high output code but, if Vref = AVDD, the output may not clamp to all 1s. The reason for this is that the max voltage that can be output from the PGA is less than +/- AVDD. So, the PGA clamps the voltage to a value which is less than Vref and hence, the modulator does not see an overvoltage.
Thanks and Best Regards,
Chris