For knowledge, there is FAQ: “How do we limit the MCLK Output frequency on the HDMI Receivers?” https://ez.analog.com/docs/DOC-2826
This function use registers DPLL.0xD3..0xD5,0xCF – description is absent in registers map DPLL/AFE…
Alexander
For knowledge, there is FAQ: “How do we limit the MCLK Output frequency on the HDMI Receivers?” https://ez.analog.com/docs/DOC-2826
This function use registers DPLL.0xD3..0xD5,0xCF – description is absent in registers map DPLL/AFE…
Alexander