Hi Miguel,
I've found a way to add an external driver (74LVC240) on the SPI clock coming from the FPGA to the DDS. In appearance, the problem seems to be solved, even though the improvement in rising/falling time is not so big.
During the next week, we'll perform a climatic test on the system, in order to be confident about the effectiveness of this solution.
Thank You very much for your support,
Fabrizio Lucini