Hi Lakshmi,
Thank you for the inputs.
On the AD7609 dataheet, Table 3 p.8, there is a timing for the Data Access Time after /RD falling edge, which vary according to the level of Vdrive. This timing were specify for a max capacitive load of 20pF.
This means that between the ADC and the processor, it needs to consider the access time, capacitive load and set up time of the processor sampling. Now if the capacitive load between the ADC and the DSP is greater than 20pF, or require longer set up time prior to the processor sampling, then there is a neeed to change the timing.
Regards,
Jonathan
