Hi Craig,
Thank you so much for replying to my question about the DSP Programming.
I am sorry to reply to your answer late, because I took much time to learn and to compare your answers and the answers (from Jithul) for my last post and to check my testing result.
By studying the answers and checking my past testing note, and the new check, I think the most possible reason for the failed boards (so far) could be the system clock speed the both answers mentioned. On our DSP board, we use 25 MHz crystal, and for my testing, I set the PLLM as 6 to generate 150MHz CCLK. In the default Kernel, it sets PLLD as 16 to generate 266MHz with 16.625 MHz crystal. For answering my last posted questions, Jithul gave me the modified 479_spi.asm. When I checked the DSP boards, I used two codes: one is Checking Code that just generates pulses per Flag0; another is Testing Code that checks every the DSP peripheral functions we are using. Every time, I checked five new DSP boards as a group. Last Wednesday, I checked the five boards with the Checking Code and its Loader uses the modified 479_spi.asm (Ext Mem Bypass) Jithul gave me, and all the five boards passed check. Then I checked the same boards with Testing Code that used the modified 479_spi as its Kernel at the beginning, but when I found it could not test the external SDRAM, I used the original Kernel. And then one of the programmed DSP boards got failed. Today, I checked five more new boards. This time I used the modified Kernel with the Testing Code but skipping the SDRAM check, so far all the boards passed the test. I have checked four groups. Only the newest group got passed to all.
Now I wanted check more boards to confirm my guess (I really appreciate it should you give any comment about it.) And I want to also modified the 479_spi for generating 150HMz CCLK with the 25MHz CLKIN, and for operating the external SDRAM. I think I just need to change the PLLD in the asm code from 16 onto 6, but I haven't reached the Assembly code of the DSP, so I am not sure if my point is correct. Besides, I can't make the 479_spi.asm pass the Project Build up to now. When I created the project for 479_spi.asm, it also generated an asm main file as followed:
I think I need put the modified 479_spi.asm into the main, but don't know how to do it (just put all the asm code into the "/*begin adding your custom code here.*/" ?). When I do the Project Build for the only 479_spi.asm, I got the error as followed:
Would you please give me some advices to modify the 479_spi.asm for generating 150MHz CCLK and for operating the SDRAM and make it pass the Project Build. (by the way, in my Testing Code, I initiate the System CLK and SDRAM CLK as followed:
"ADSP_2147x_2148x_PLL_Init(6,2,0,2);" and
"ADSP_369_2137x_2147x_2148x_SDRAM_Init(
0,
B0SD,
SDCL3|SDTRAS4|SDTRP2|SDPM|SDCAW8|SDPSS|X16DE|SDTWR1|SDTRCD2|SDRAW12|SDPGSZ|0|SDADDRMODE,
0x243,
2,
0x200000
);"
they are correct?)
I need to study the Assembly of the DSP and about the Kernel soon.
Should you need any other information about my question, please let me know.
Thanks again,
Ning