Ah I was probing the wrong pin. But I am probing directly on the via's next to the BGA balls. There is no SPI clk noise on VDDA1P3_BB, but it does drop about 10mV with a transient when the bbpll starts to be configured. After that, I noticed very small transients every half second on the pin that would ring 1.31 to 1.27V.
I added a large capacitor directly to the 1.3V via and increased the size of the bypass capacitor located next to the chip for this power pin, and now I am unable to detect the transients, other than the 10mV drop when BBPLL becomes enabled, I presume due to a current draw increase. So the pin now stays within the 2.5% specification, but is still unable to lock...
I am currently using a sine wave for the reference clock, so no ringing. I don't expect it to have the best performance, but it locks just fine on the evaluation board.
I have also tried a square wave as well, with around +-10% ringing.