Hi Tarzan,
The ADP2164 tracking was tested in lab with ADP2164 eval board, 600KHZ and 1.2MHZ, Vin=5V, Vmaster=3.3V, the rising time for the master voltage = 8ms, Vslave=1.2V, Rtop=10k@1%, Rbot=10k@1%, Rtrakt=10k@1%, Rtrakb=10k@1%, The screen shot is as follows:
The internal error amplifier has three positive inputs: Vref, the soft start voltage and the TRK voltage. The error amplifier regulates the FB voltage to the lowest of the three voltages. Tracking is not effective if the TRK voltage rises too fast ( when the voltage at TRK pin is above 0.6V), the soft start voltage will regulate the output voltage.
From the figure in your file, we can see that the rising time of Vslave is not controlled by TRK voltage, and there is a time delay between Vmaster and Vslave starting to rise. Also it looks like the rising time for Vslave is about 15ms, which is much longer than 2048 clock cycles set by the internal soft start. Is there a delay set for different channels of the oscilloscope? The scales of time are the same? Could you show how Vmaster, Rtrkt and Rtrkb are connected on the board?
Hong