A star configuration can work. For SDTV we are only talking 27MHz clocks which is not a problem for the FPGA. The real question is what do you gain by doing it this way. If all you are doing is compressing a SD signal then you don't have to route or use the extra input and output pins on the FPGA for the bus between the 7188 and the 212. If you need access to this bus then it is the way to go.
The 7188 does not have a de-interlacer.
I think we'll need a little better definition of exactly what you want your system to do.
- Input resolutions
- Output formats (compressed, raw, interlaced, progressive)
- Any special functions or features you need.