Hi,
Apologies for the delayed response. As you know, the stand-alone mode operation is further described on the page 3-4 of the user guide. The eval board has a gate array (U10 on the eval board) which provides the necessary control signals in standalone or with the CED. In stand-alone mode, the gate arrays flexible logic buffers the ADC data according to the read data mode configuration (word or byte) and it offers the flexibility of applying externally generated control signals via SMB connector (for /CNVST). There are also test points for other control signals but you have to ensure that the gate array is isolated and it could take some work, looking at the schematics. Do you intend to use your microcontroller for both control signals and reading of conversion data?
Make sure that the JP9 (DVDD) and JP19 (AVDD) are +5V and other supplies on board are ok. The power needs to be supplied through the two power supply blocks SJ1 (AVDD) and SJ2 (DVDD, OVDD) in standalone mode. In standalone mode, when the CONTROL input to the gate array is LOW, which is pulled down by default, the gate array provides the necessary signals for conversion and buffers the conversion data. In serial reading mode, the default settings are Master Read during Conversion Mode using the internal ADC serial clock. Serial data is available at T3, T4, T5 and T6 for SDOUT, SCLK, SYNC and RDERROR respectively. Buffered serial data is output on the three test points TP17, TP18 and TP19 for SCLK, SYNC, and SDOUT respectively. For serial reading mode, S16 allows the selection of: choice of inverting SCLK and SYNC, and choice of using internal or external (slave mode) SCLK. When using Slave Serial Mode, the external serial clock SCLK applied to the ADC is the MCLK, U12, frequency (40MHz).
Regards,
Karen