Hi Nick,
Thanks for the details. I understand your problem, but without looking into code flow, we cannot get clear understanding of issue.
BTW, do you have synchronisation instructions (ssync()) at the end of ISR? As you know, most of the times, we clear the interrupt latch bit in ISR. If we exist from ISR immediately after it, and if the latch bit do not clear properly before it, then we may see a false interrupt, sometimes. So, generally we use ssync instructions to aviod it. Can you try this, if not done earlier?
Also, how many IVG levels are enabled in your case? If there any IVG level free, can you try assigning it to MDMA only (as you see problem with MDMA interrupt only)? Let me know if you need more details.