I understand where you are coming from and these pictures do offer some insights, but there is no substitute for knowing what is going on at the signal level. The "flying lead" approach has worked for some prototype projects but can be sensitive to EMI and have higher levels of series inductance, which can combine with gate capacitance to ring when there is no edge rate control. Your original plots on the SPI signals showed quite a bit of noise, but that could be an artifact of the probing approach. In similar cases, we have found that the power source is the most common issue. Once we know that VDD is solid during the critical times, we would turn our attention to the signal integrity on the SPI lines. In addition to this discussion, we have already arranged for you and your team to borrow an EVAL-ADIS to assist you in this process. This may help in device validation and if needed, we have some insights that might enable remote connection through J1. Don't do this without consulting us; we can save you some time!
Look forward to helping when more insights are available.
Best,
NevadaMark