Generally I would expect DDS to be a fine solution for generating a clock for an FPGA from a jitter performance perspective. Given the range of frequency you are looking to support, DDS is probably the best solution. AD9852 should be a very good fit for this. If you use a sample clock of 300 MHz, then you can get steps as small as 70 milliHertz - I consider that very small, hopefully it is small enough for your needs.
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